Electronic components such as transistors, MEMs, diodes, or more complex integrated circuits are manufactured from semiconductor wafers using chemical processing techniques. Packaging of the devices is done by encapsulating the devices with protective covers while providing for physical connections between the device and the environment. Examples of physical connections include;                Electrical connection to provide current or voltage for device operation        Thermal connection to dissipate heat from the device        Optical connection to extract light from devices such as light emitting diodes, or to provide light for devices such as image sensors        To provide a physical connection to the device for measurement of external physical parameters such as pressure, temperature, humidity, acceleration, rotation, ambient light, etc.        
State of art methods to package devices include                Connecting the device to metal lead frames and over molding with a polymer        Connecting the device to a polymer, glass fiber or ceramic substrate and over molding with a polymer        Chip scale packaging where the device electrical connections are extended using an overlay of deposited metal and protective polymer coating        
These methods suffer from high production cost, large form factor and poor dissipation of the heat generated during the operation of the device. The heat dissipation of electronic devices is a major impediment in next generation electronics. As the density of components increases, the energy density increases. To prevent component failures enhanced heat dissipation is required. Most packaging technologies provide heat dissipation from only one side of the semiconductor chip. For example, in plastic molded packages the heat dissipation is provided by a copper slug located in the bottom side of the package. Wafer level packaging also provides more solutions for packaging electronic components. In wafer level packaging, a semiconductor wafer is laminated with layers of electrically isolating material intermixed with electrically conducting paths. The electrically conducting paths are designed by choice of material and dimensions of the electrical conducting paths for connection by a surface mount technology (SMT) to a printed circuit board (PCB). The electrical isolating layers are poor conductors of heat. As a result, standard wafer level packaging does not provide for efficient heat conduction from the electronic device. Patent Cooperation Treaty publication WO/2014/064541 to the same assignee discloses a wafer level package for LED devices where the heat conduction of the package is enhanced by creating thermal vias in the package. Patent Cooperation Treaty publication WO/2014/064541 to the same assignee describes a semiconductor package which provides for heat dissipation in one direction. For other electronic devices and specifically for power electronic devices, where the amount of generated heat is very large it is desirable to maximize the heat conductance from the device to maintain a reasonable device operating temperature. One method of enhancing the heat dissipation includes providing thermal vias in more than one direction. However providing thermal vias in more than one direction and specifically providing thermal vias in more than one direction in state of art wafer level package poses a technical challenge. Hence an alternative packaging of electronic components is desired which can provide superior heat dissipation, small form factor and low cost.
Glossary
Wafer as used in the current disclosure means a semiconductor, polymer, metal, glass, quartz, or ceramic wafer used for the packaging of electronic devices. The wafer is typically round with a diameter of 150, 200, 300 or 450 mm and thickness of 200 micron to 1000 micron.
Semiconductor device as used in the current disclosure means an electronic, optoelectronic, electromechanical device or a device having an electronic connection either for operation or for readout of a physical parameter. The semiconductor device has a semiconductor constituent composed of semiconducting materials such as Silicon, GaAs, GaN, InP and is manufactured using chemical processing methods.
Die as used in the current disclosure means a single unit of a semiconductor device. The device can also include discreet components such as capacitor, resistor, or inductor.
Bottom face as used in the current disclosure means the surface of the semiconductor device which is nominally on the bottom side of the device
Top face as used in the current disclosure means the surface of the semiconductor device which is nominally on the top side of the device and located opposite the bottom face
Electrical pad as used in the current disclosure means a metal coated or otherwise conducting enclosed area located on the semiconductor device top or bottom face, which provides an electrical connection into the semiconductor device
Thermal pad as used in the current disclosure means an enclosed area located on the top or bottom face of the semiconductor device and adjacent to a heat generating volume of the semiconductor device.
Metal pad as used in the current disclosure means an enclosed area on the semiconductor device covered with a metal layer such as Aluminum, Copper, Gold, Nickel, Titanium, Chrome, Silver or combinations thereof or other metal layers, which can be used as either a thermal pad or an electrical pad.
Conducting region as used in the current disclosure means a region conducting either thermal or electrical flow
Top cover wafer as used in the current disclosure means a wafer used to cover the top face of the semiconductor device
Bottom cover wafer as used in the current disclosure means a wafer used to cover the bottom face of the semiconductor device
Cover wafer as used in the current disclosure means a either a top or bottom cover wafer
Via as used in the current disclosure means a pass through hole from one face of a wafer to the second opposing face of the wafer.
Internal Face as used in the current disclosure means the surface of the wafer to which semiconductor devices are attached.
External face as used in the current disclosure means the surface of the wafer which is opposing the internal face